Int.ernational Conference Papers

  year       vol.  
  month Title Author(s) Conference, Inst. pages  
1 1975 A survey: Generating all the cycles of a graph Shuji Tsukiyama, Isao Shirakawa, Hiroshi Ozaki Proc. 2nd USA-JAPAN Computer Conf.,AFIPS & IPSJ    
8 pp.92-96
2 1977 An algorithm for the via assignment problem in multilayer backboard wiring Shuji Tsukiyama, Isao Shirakawa, Shigeo Asahara Proc. Int. Symp. Circuits and Systems,IEEE    
4 pp.156-159
3 1979 An algorithm for single-row routing with prescribed street congestions Shuji Tsukiyama, Ernest S. KuhIsao Shirakawa Proc. Int. Symp. Circuits and Systems,IEEE & IECEJ    
7 pp.466-469
4 1979 Algorithm to enumerate all the cutsets in O(|V|+|E|) time per cutset Shuji Tsukiyama, Hiromu Ariyoshi, Isao Shirakawa Proc. Int. Symp. Circuits and Systems,IEEE & IECEJ    
7 pp.645-648
5 1981 On the layering problem of multilayer PWB wiring Shuji Tsukiyama, Ernest S. Kuh, Isao Shirakawa Proc. 18th DA Conf.,ACM & IEEE    
7 pp.738-745
6 1982 An algorithm of global routing for master slice LSI Shuji Tsukiyama, Ikuo Harada, Masahiro Fukui, Isao Shirakawa, Hiroshi Ozaki Proc. Int. Symp. Circuits and Systems,IEEE    
5 pp.1009-1012
7 1983 On the computational complexity of an external pin assignment problem Shuji Tsukiyama, Tsutomu Kimoto, Isao Shirakawa Proc. European Conf. Circuit Th. & Design,ECCTD Steering Committee    
9 pp.195-197
8 1983 Placement and routing algorithms for gate array LSI Shuji Tsukiyama, Ikuo Harada, Masahiro Fukui, Isao Shirakawa Proc. Int. Conf. Computer Design: VLSI in Computers,IEEE    
11 pp.596-599
9 1984 A heuristic algorithm for a pin assignment problem of gate array LSI's Shuji Tsukiyama, Masahiro Fukui, Isao Shirakawa Proc. Int. Symp. Circuits and Systems,IEEE    
5 pp.465-469
10 1985 On a second shortest k-tuple of edge-disjoint paths Shoji Shinoda, Shuji Tsukiyama, Isao Shirakawa, Koichi Omura Proc. European Conf. Circuit Th. & Design,ECCTD Steering Committee    
9 pp.29-32
11 1986 An algorithm to enumerate all complex triangles in a maximal planar graph for use in VLSI floor-plan Shuji Tsukiyama, Keiichi Koike, Isao Shirakawa Proc. Int. Symp. Circuits and Systems,IEEE    
5 pp.321-324
12 1986 A switch-box router -- Tree-ring switch-box router Yoshiyuki Kawakami, Shuji Tsukiyama, Isao Shirakawa, Hiroshi Ozaki Proc. 1986 Joint Tech. Conf. Circuits and Systems,KIEE & IECEJ    
10 pp.55-62
13 1987 An algorithm generating all rectangular duals for VLSI floor-plan Shuji Tsukiyama, Katsunori Tani, Isao Shirakawa Digests of Tech. Papers 1987 Symp. on VLSI Circuits,IFIP    
5 pp.15-16
14 1987 On overlapping territories satisfying cardinality constraints Takashi Moriizumi, Shuji Tsukiyama, Shoji Shinoda, Masakazu Sengoku, Isao Shuirakawa Proc. '87 Korea Automation Control Conf.,韓国自動制御協議会 2  
10 pp.857-862
15 1988 An optimal cardinality-constrained territory map on a network Takashi Moriizumi, Shuji Tsukiyama, Shoji Shinoda, Masakazu Sengoku Proc. Int. Symp. Circuits and Systems,IEEE    
6 pp.1541-1544
16 1988 Area-efficient drawings of rectangular duals for VLSI floor-plan Katsunori Tani, Shuji Tsukiyama, Isao Shirakawa, Hiromu Ariyoshi Proc. Int. Symp. Circuits and Systems,IEEE    
6 pp.1545-1548
17 1988 Lower bounds to the area required to draw a rectangular dual Katsunori Tani, Shuji Tsukiyama, Shoji Shinoda, Isao Shirakawa Abstracts 13th Int. Symp. Math. Prog.,Math. Prog. Soc. & Oper. Res. Soc.    
8 p.338
18 1988 An expert system for mask pattern generator of CMOS logic cells Akihisa Yamada, Isao Shirakawa, Shuji Tsukiyama, Shoni Shinoda Proc. Joint Tech. Conf. Circuits/Systems Comp. & Comm.,KITE CAS Soceity, IEICE CAS Tech. Group, IEEE CAS Society    
11 pp.299-304
19 1988 A floor-plan system using a rectangular dual Katsunori Tani, Shuji Tsukiyama, Isao Shirakawa Proc. Joint Tech. Conf. Circuits/Systems Comp. & Comm.,KITE CAS Soceity, IEICE CAS Tech. Group, IEEE CAS Society    
11 pp.310-315
20 1989 A condition for a maximal planar graph to have a unique rectangular dual and its application to VLSI floor-plan Shuji Tsukiyama, Toshiyuki Maruyama, Shoji Shinoda, Isao Shirakawa Proc. Int. Symp. on Circuits and Systems,IEEE    
5 pp.931-934
21 1989 An algorithm to detect positive cycles in a constraint graph for layout compaction Kunihiko Ishima, Shuji Tsukiyama Proc. 1989 Joint Tech. Conf. Circuits/Systems Comp. & Comm.,IEICE CAS Tech. Group, KITE CSCC Society, IEEE CAS Society    
6 pp.522-526
22 1989 An expert system for mask pattern generator of CMOS logic cells Isao Shirakawa, 4 Proc. European Conf. Circuit Th. & Design,ECCTD Steering Committee    
9 pp.324-328
23 1990 A consideration on a sliding palette problem in a two-dimensional automatic warehouse Akio Sakamoto, Shuji Tsukiyama, Kenji Shimizu Proc. Int. Symp. on Circuits and Systems,IEEE    
5 pp.2849-2852
24 1990 An algorithm to detect positive cycles in a constraint graph for layout compaction Kunihiko Ishima, Shuji Tsukiyama, Shoji Shinoda Proc. Int. Symp. on Circuits and Systems,IEEE    
5 pp.2853-2856
25 1990 A floorplanning system using a rectangular dual Katsunori Tani, Shuji Tsukiyama, Isao Shirakawa, Shoji Shinoda Proc. 1990 Bilkent Int. Conf. on New Trends in Comm., Control, & Signal Processing,Bilkent Univ. Ankara, Turkey    
7 pp.1227-1233
26 1990 On the minimum number of sliding operations of palettes in a two-dimensional automatic warehouse Shigeo Matsuki, Shuji Tsukiyama, Akio Sakamoto Proc. 1990 Joint Tech. Conf. on Circuits/Systems Comp. & Comm.,KITE CSCC Society, IEICE CAS Tech. Group, IEEE CAS Society    
12 pp.191-196
27 1991 An improvement of a state encoding algorithm for sequential circuits Nobuhiko Ito, Harunowo, Shuji Tsukiyama Proc. 1991 Joint Tech. Conf. Circuits/Systems Comp. & Comm.,IEICE CAS Tech. Group, KITE CSCC Society, IEEE CAS Society    
12 pp.307-311
28 1996 A VLSI architecture for MPEG2 MP@HL real time motion estimator T.Onoye, G.Fujita, I.Shirakawa, K.Matsumura, H.Ariyoshi, S.Tsukiyama Proc. Int. Symp. on Circuits and Systems,IEEE    
5 pp.664-667
29 1996 VLSI Implementation of Hierarchical Motion Estimator for MPEG2 MP@HL T.Onoye, G.Fujita, I.Shirakawa, K.Matsumura, H.Ariyoshi, S.Tsukiyama Proc. IEEE 1996 Custom Integrated Circuits Conf.,IEEE    
5 pp.351-354
30 1996 A new algorithm for p-collection problem on a tree-type flow network Shuji Tsukiyama Proc. 1996 Int. Tech. Conf. on Circuits/Systems, Computers and Communications    
7 pp.721-724
31 1996 Implementation of half-pel precision motion estimator for MPEG2 MP@HL G.Fujita, T.Onoye, I.Shirakawa, S.Tsukiyama, K.Matsumura Proc. IEEE Region 10 International Conference on Digital Signal Processing Applications (TENCON'96)    
11 pp.949-954
32 1997 Not necessarily more switches more routability Yu-Liang Wu, Douglas Chang, Malgorzata Marek-Sadowska, Shuji Tsukiyama Proc. Asia and South Pacific Design Automation Conf.    
1 pp.579-584
33 1997 A positioning problem of fictitious terminals for a parallel router based on area division Atsushi Kamoshida, Shuji Tsukiyama Proc. Int. Symp. on Circuits and Systems    
6 pp.1556-1559
34 1998 A delay minimization router:(TD)^2 router K.Baba, N.Tsujii, K.Yamamoto, S.Tsukiyama Proc. 1998 IEEE Asia-Pacific Conf. on Circuits and Systems,IEEE Circuits and Systems Society    
11 pp.117-120
35 2000 An interconnect topology optimization by a tree transformation N.Tsujii, K.Baba, S.Tsukiyama Proc. Asia and South Pacific Design Automation Conf.,IEEE Circuits and Systems Society, ACM SIGDA    
1 pp.93-98
36 2000 A new statistical static timing analyzer considering correlation between delays Shuji Tsukiyama, Masakazu Tanaka, Masahiro Fukui Proc. ACM/IEEE Int. Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU2000),SIGDA, ACM    
12 pp.27-33
37 2001 A statistical static timing analysis considering correlations between delays Shuji Tsukiyama, Masakazu Tanaka, Masahiro Fukui Proc. Asia and South Pacific Design Automation Conf.,IEEE CAS Society, ACM SIGDA    
3 pp.353-358
38 2001 Two-dimensional array layout for low power NMOS 4-phase dynamic logic Makoto Furuie, Takao Onoye, Shuji Tsukiyama, Isao Shirakawa Proc. 2001 Int. Conf. of Electronics Packaging (2001 ICEP),Japan Inst. of Electronics Packaging    
5 pp.417-421
39 2001 Two-dimensional array layout for nMOS 4-phase dynamic logic Makoto Furuie, Takao Onoye, Shuji Tsukiyama, Isao Shirakawa Proc. Int. IEEE Conf. on Electronics, Circuits, and Systems (ICECS 2001),IEEE Circuits and Systems Society    
9 pp.589-592
40 2001 Techniques to remove false paths in statistical static timing analysis Shuji Tsukiyama, Masakazu Tanaka, Masahiro Fukui Proc. Int. Conf. on ASIC (ASICON 2001),Chinese Inst. of Electronics    
10 pp.39-44
41 2002 False paths elimination in statistical static timing analysis Masaki Uehata, Masakzu Tanaka, Masahiro Fukui, Shuji Tsukiyama Proc. 2002 Int. Tech. Conf. on Circuits/ Systems, Computers and Communications,Engineering Sciences Society, IEICE    
7 pp.357-360
42 2002 Distribution of critical path delays in a combinatorial circuit Daigo Yanagi, Shuji Tsukiyama Proc. 2002 Int. Tech. Conf. on Circuits/ Systems, Computers and Communications,Engineering Sciences Society, Inst. of Electronics, Information and Communication Engineers    
7 pp.1300-1303
43 2002 Parasitic capacitance modeling for multilevel interconnects S.Tani, Y.Uchida, M.Furuie, S.Tsukiyama, B.Y.Lee, S.Nishi, Y.Kubota, I.Shirakawa, S.Imai Proc. Asia-Pacific Conference on Circuits and Systems 2002 (APCCAS2002),IEEE Circuits and Systems Society    
12 pp.59-64
44 2003 System-on-panel design of digital halftoning processor for TFT liquid crystal display M.Furuie, F.Lu, B.Y.Lee, T.Onoye, S.Tsukiyama, S.Nishi, Y.Kubota, I.Shirakawa, S.Imai International Signal Processing Conference, Global Technology Conferences   CD-ROM
4
45 2003 A parasitic capacitance modeling method for non-planar interconnects S.Tani, Y.Uchida, M.Furuie, S.Tsukiyama, B.Y.Lee, S.Nishi, Y.Kubota, I.Shirakawa, S.Imai Proc. Synthesis and System Integration of Mixed Information Technologies (SASIMI 2003),Steering Committee for Synthesis and System Integration of Mixed Information Technologies    
4 pp.294-299
46 2003 Parasitic capacitance modeling for on-chip interconnects Y.Uchida, S.Tani, S.Tsukiyama, I.Shirakawa Proc. 2003 Int. Tech. Conf. on Circuits/ Systems, Computers and Communications,Engineering Science Society, IEICE    
7 pp.1638-1641
47 2003 Parasitic capacitance modeling for TFT liquid crystal displays Y.Uchida, S.Tani, S.Tsukiyama, I.Shirakawa Proc. European Solid State Device Research Conf. (ESSDERC 2003),IEEE Electron Devices Society    
9 pp.453-456
48 2004 Toward stochastic design for digital circuits -- Statistical static timing analysis -- Shuji Tsukiyama Proc. Asia and South Pacific Design Automation Conf. 2004,IEEE CAS Society, ACM SIGDA    
1 pp.762-767
49 2005 Interconnect capacitance extraction for system LCD circuits Y. Uchida, S. Tani, M. Hashimoto, S. Tsukiyama, I. Shirakawa Proc. IEEE/ACM Great Lake Symposium on Very Large Scale Integrated circuits (GLSVLSI 2005),ACM SIGDA    
4 pp.160-163
50 2005 A design scheme for sampling switch in active matrix LCD Shingo Takahashi, Akira Taji, Shuji Tsukiyama, Masanori Hashimoto, Isao Shirakawa Proc. European Conference on Circuit Theory and Design (ECCTD 2005),European Circuits Society    
8 p.3E212
51 2005 A sampling switch design for liquid crystal displays Shingo Takahashi, Shuji Tsukiyama, Masanori Hashimoto, Isao Shirakawa IEEE Tencon'05,IEEE IEEE Region 10 (1C-03.3)  
11
52 2006 An algorithm for calculating correlation coefficients between Elmore interconnect delays Shuji Tsukiyama, Masahiko Tomita Proc. 2006 IEEE Int. Symp. on Circuits and Systems (ISCAS 2006),IEEE Circuits and Systems Soceity    
5 pp.2069-2072
53 2006 Transistor sizing of LCD driver circuit for technology migration T. Ijichi, M. Hashimoto, S. Takahashi, S. Tsukiyama, I. Shirakawa Proc. of Int. Tech. Conf. on Circuits/Systems, Computers and Communications (ITC-CSCC),The Electrical Engineering/Electronics, Computer, Telecommunications and Information Association (ECTI), Thailand 1  
7 pp.125-128
54 2007 A power grid optimization algorithm by direct observation of timing error risk reduction Makoto Terao, Kenji Kusano, Yoshiyuki Kawakami, Masahiro Fukui, Shuji Tsukiyama Proc. of the 14th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2007),SASIMI Steering Committee    
10 pp.310-315
55 2008 A design method of finding optimal sampling pulses and transistor sizes in a sampling circuit for liquid crystal displays Shingo Takahashi, Shuji Tsukiyama, Masanori Hashimoto, Isao Shirakawa Proc. of the 23rd Int. Tech. Conf. on Circuits/Systems, Computers and Communications,Engineering Science Society, IEICE    
7 pp.197-200
56 2008 A power grid optimization algorithm with observation of timing error risk by IR drop Yoshiyuki Kawakami, Masahiro Fukui, Shuji Tsukiyama Proc. IASTED Int. Conf. on Circuits and Systems,Int. Assoc. of Sci. & Tech. for Development -625  
8 pp.37-42
57 2008 Power grid optimization with consideration of timing violation by IR drop Yoshiyuki Kawakami, Masahiro Fukui, Shuji Tsukiyama Proc. 2008 International SoC Design Conference,The Inst. of Electronics Engineers of Korea    
11 pp.109-112
58 2008 A new statistical timing analyzer propagating delay and slew distributions simultaneously Shingo Takahashi, Shuji Tsukiyama Proc. 2008 IEEE Asia Pacific Conference on Circuits and Systems,IEEE Circuits and Systems Society    
12 pp.352-355
59 2009 A Gaussian mixture model for propagating distributions of delay and slew together Shingo Takahashi, Shuji Tsukiyama ACM Int. Workshop on Timing Issues in the Specification and Synthesis of Digital Systems(TAU 2009) Session I-2  
2 pp.5-10
60 2009 A Gaussian mixture model to propagate delay and slew distributions together in statistical timing analysis Shingo Takahashi, Shuji Tsukiyama Proc. the 15th Workshop on Synthesis And System Integration of Mixed Information technologies(SASIMI 2009),SASIMI Steering Committee   R1-11
3 pp.70-75
61 2009 A Gaussian mixture model for statistical timing analysis Shingo Takahashi, Yuki Yoshida, Shuji Tsukiyama Proc. the 46th Design Automation Conf.,The Association for Computing Machinery    
6 pp.110-115
62 2009 A new power grid optimization algorithm based on manufacturing cost restriction Takayuki Hayashi, Masahiro Fukui, Shuji Tsukiyama ECCTD Steering Committee    
8 pp.703-706
63 2009 Accuracy of the criticality probability of a path in statistical timing analysis Shuji Tsukiyama, Masahiro Fukui ECCTD Steering Committee    
8 pp.707-710
64 2009 Statistical static timing analysis – What we have ever seen – Shuji Tsukiayma Proc. Japan Conf. on Computational Geometry and Graphs (JCCGG2009)   invited
11 p.117