Papers in English

  year       vol. (no.)
  month Title Author(s) Journal, Inst. pages
1 1977 A new algorithm for generating all the maximal independent sets Shuji Tsukiyama, Mikio Ide, Hiromu Ariyoshi, Isao Shirakawa SIAM J. Comput.,SIAM 6(3)
9 pp.505-517
2 1979 An algorithm for the via assignment problem in multilayer backboard wiring Shuji Tsukiyama, Isao Shirakawa, Shigeo Asahara IEEE Trans. CAS,IEEE CAS-26(6)
6 pp.369-377
3 1980 An algorithm for single-row routing with prescribed street congestions Shuji Tsukiyama, Ernest S. Kuh, Isao Shirakawa IEEE Trans. CAS,IEEE CAS-27(9)
9 pp.765-772
4 1980 An algorithm to enumerate all cutsets of a graph in linear time per cutset Shuji Tsukiyama, Isao Shirakawa, Hiroshi Ozaki, Hiromu Ariyoshi J. ACM,ACM 27(4)
10 pp.619-632
5 1982 Double-row planar routing and permutation layout Shuji Tsukiyama, Ernest S. Kuh Networks,John Wiley & Sons 12(3)
pp.287-316
6 1983 On the layering problem of multilayer PWB wiring Shuji Tsukiyama, Ernest S. Kuh, Isao Shirakawa IEEE Trans. CAD,IEEE CAD-2(1)
1 pp.30-38
7 1983 A new global router for gate array LSI Shuji Tsukiyama, Ikuo Harada, Masahiro Fukui, Isao Shirakawa IEEE Trans. CAD,IEEE CAD-2(4)
10 pp.313-321
8 1987 On a second shortest k-tuple of edge-disjoint paths Shoji Shinoda, Shuji Tsukiyama, Isao Shirakawa Trans. of IEICE,IEICE E70(10)
10 pp.945-950
9 1991 A consideration on a sliding palette problem in a two-dimensional automatic warehouse Kenji Shimizu, Akio Sakamoto, Shuji Tsukiyama, Mitsuru Numata, Takashi Kawabata IEICE Trans. on Fundamentals of Elec., Comm. & Comp. Sci.,IEICE E74(4)
4 pp.644-652
10 1991 A dynamic algorithm for placing rectangles without overlapping Takeshi Tokuyama, Takao Asano, Shuji Tsukiyama J. Info. Processing,IPSJ 14(1)
4 pp.30-35
11 1991 On an area-efficient drawings of rectangular duals for VLSI floor-plan Katsunori Tani, Shuji Tsukiyama, Isao Shirakawa, Shoji Shinoda Mathematical Programming Series B,North-Holland 52
6 pp.29-43
12 1992 A hierarchical multi-layer global router Masayuki Hayashi, Hiroyoshi Yamazaki, Shuji Tsukiyama, Nobuyuki Nishiguchi IEICE Trans. on Fundamentals of Elec., Comm. & Comp. Sci.,IEICE E74(11)
11 pp.1294-1300
13 1992 On an algorithm to detect positive cycles in a constraint graph for layout compaction Kunihiko Ishima, Shuji Tsukiyama IEICE Trans. on Fundamentals of Elec., Comm. & Comp. Sci.,IEICE E74(11)
11 pp.3613-3616
14 1995 A hybrid hierarchical global router for multi-layer VLSI's Masayuki Hayashi, Shuji Tsukiyama IEICE Trans. on Fundamentals of Elec., Comm. & Comp. Sci.,IEICE E78-A(3)
3 pp.337-344
15 1996 Graph based analysis of 2-D FPGA routing Yu Liang Wu, Malgorzata Marek-Sadowska, Shuji Tsukiyama IEEE Trans. CAD/ICAS,IEEE 15(1)
1 pp.33-44
16 1998 A new algorithm for p-collection problem on a tree-type flow network Shuji Tsukiyama IEICE Trans. on Fundamentals of Elec., Comm. & Comp. Sci.,IEICE E81-A(1)
1 pp.139-146
17 1998 On improved FPGA greedy routing architectures Yu Liang Wu, Douglas Chang, Malgorzata Marek-Sadowska, Shuji Tsukiyama IEICE Trans. Fundamentals,IEICE E81-A(12)
12 pp.2485-2491
18 1999 Generation of minimal separating sets of a graph Jiro Hayakawa, Shuji Tsukiyama, Hiromu Ariyoshi IEICE Trans. on Fundamentals of Elec., Comm. & Comp. Sci.,IEICE E82-A(5)
5 pp.775-783
19 1999 An algorithm to position fictitious terminals on borders of divided routing areas Atsushi Kamoshida, Shuji Tsukiyama IEICE Trans. Fundamentals,Inst. Electronics, Information and Communication Engineers E82-A(11)
11 pp.2424-2430
20 2001 An algorithm for statistical static timing analysis considering correlations between delays Shuji Tsukiyama, Masakazu Tanaka, Masahiro Fukui IEICE Trans. Fundamentals,Inst. of Electronics, Information and Communication Engineers E84-A(11)
10 pp.2746-2754
21 2002 An interconnect topology optimization by tree transformation Itthichai Arungsrisangchai, Shuji Tsukiyama, Isao Shirakawa J. of Japan Inst. of Electronics Packaging,Japan Institute of Electronics Packaging 5(4)
7 pp.342-348
22 2003 A parasitic capacitance modeling method for non-planar interconnects in liquid crystal displays S.Tani, Y.Uchida, M.Furuie, S.Tsukiyama, B.Y.Lee, S.Nishi, Y.Kubota, I.Shirakawa, S.Imai IEICE Trans. Fundamentals,IEICE E86-A(12)
12 pp.2923-2932
23 2006 An algorithm to calculate correlation coefficients between interconnect delays for use in statistical timing analysis Shuji Tsukiyama, Masahiko Tomita IEICE Trans. Fundamentals,IEICE E89-A(2)
2 pp.535-543
24 2006 A sampling switch design procedure for active matrix liquid crystal displays Shingo Takahashi, Shuji Tsukiyama, Masanori Hashimoto, Isao Shirakawa IEICE Trans. Fundamentals,IEICE E89-A(12)
12 pp.3538-3545
25 2007 Transistor sizing of LCD driver circuit for technology migration Masanori Hashimoto, Takahito Ijichi, Shingo Takahashi, Shuji Tsukiyama, Isao Shorakawa IEICE Trans. Fundamentals,IEICE E90-A(12)
12 pp.2712-2717
26 2008 A power grid optimization algorithm by observing timing error risk by IR drop Yoshiyuki Kawakami, Makoto Terao, Masahiro Fukui, Shuji Tsukiyama IEICE Trans. Fundamentals,IEICE E91-A(12)
12 pp.3423-3430
27 2009 A new statistical timing analysis using Gaussian mixture models for delay and slew propagated together Shingo Takahashi, Shuji Tsukiyama IEICE Trans. Fundamentals,IEICE E92-A(3)
3 pp.900-911