English papers


  • Papers in English
  • Papers presented at International Conferences
  • Books
  • Japanese Patents
  • US Patents
  • European Patents
  • Korean Patent

  • Papers in English


    A1. Y.Sugimoto, T.Miyakawa and E.Itoh, "The Efficient Circuit Design System for Analog Integrated Circuits," IEEE Trans., Consumer Electronics, vol.CE-28, no.3, pp.463-474, August 1982.pdf

    A2. Y.Sugimoto, "A Monolithic 10-bit A/D&D/A Converter for PCM Audio Use," IEEE Trans., Consumer Electronics, vol.CE-30, no.3, pp.332-339, August 1984.pdf

    A3. M.Nakamura, Y.Sugimoto, T.Watanabe and T.Sugimoto, "A 10-bit 65MSps Glitchfree Video D/A Converter," IEEE Trans., Consumer Electronics, vol.CE-31, no.3, pp.592-600, August 1984.pdf

    A4. Y.Sugimoto and H.Mafune, "High Performance and Versatile BiCMOS Electronic Volume IC," IEICE Trans., , vol.CE71, pp.289-291, August 1988.pdf

    A5. M.Nakamura, Y.Sugimoto, , "A 96kHz 16bit Dual Channel A/D Converter LSI for Digital Audio Applications," IEEE Trans., Consumer Electronics, vol.CE-35, no.3, pp.536-543, August 1989.pdf

    A6. Y.Sugimoto and S.Mizoguchi, "An Experimental BiCMOS Video 10-bit ADC," IEEE JSSC, vol.24, no., pp.997-999, August 1989.pdf

    A7. K.Tsugaru, "A Single-Power-Supply 10-b Video BiCMOS Sample-and-Hold IC," IEEE JSSC, vol.25, no., pp.653-659, June 1990.pdf

    A8. Y. Sugimoto, "A Study of a MOS VCO Circuit by using a Current-Controlled Differential Delay Cell," IEICE Trans. Fundamentals, Vol.E77-A, No.11, pp.1929-1931, November 1994.pdf

    A9. Y.Sugimoto, S.Tokito, H.Kakitani and E.Seta, "A Current-Mode Bit-Block Circuit Applicable to Low-Voltage, Low-Power Pipeline Video-Speed A/D Converters," IEICE Trans. Fundamentals, Vol.E79-A, No.2, pp.199-209, February 1996.pdf

    A10. Y.Sugimoto and T.Tsuji, "Study of a Low Voltage, Low Power and High Frequency CMOS VCO Circuit," IEICE Trans. Fundamentals, Vol.E79-A, No.5, pp.630-633, May 1996.pdf

    A11. Y.Sugimoto, T.Ueno and T.Tsuji, "Design of a Low-Voltage, Low-Power, High-Frequency CMOS Current-Mode VCO Circuit by using 0.6ƒŹm MOS Devices," IEICE Trans. Fundamentals, Vol.E80-A, No.2, pp.304-312, February 1997.pdf

    A12. Y.Sugimoto, "Basics for High-frequency Electronic Circuits," Journal of SHM, vol.13, no.3, pp.2-8, May 1997.

    A13. Y.Sugimoto, M.Sekiya and T.Iida, "A Study of the Signal-to-Noise Ratio of a High-Speed Current-Mode CMOS Sample-and-Hold Circuit," IEICE Trans. Fundamentals, Vol.E80-A, No.10, pp.1986-1993, October 1997.pdf

    A14. Y.Sugimoto and M.Sekiya, "Design of a Sub-1.5V, 20MHz, 0.1% MOS Current-Mode Sample-and-hold Circuit," IEICE Trans. Fundamentals, Vol.E81-A, No.2, pp.258-260, February 1998.pdf

    A15. Y.Sugimoto and H.Ueno, "A 2 V, 500 MHz and 3 V, 920 MHz Low-Power Current-Mode 0.6ƒŹm CMOS VCO Circuit," IEICE Trans. Electronics, Vol.E82-C, No.7, pp.1327-1329, July 1999.pdf

    A16. Y.Sugimoto, "A 1.5- V Current-Mode CMOS Sample-and-Hold IC with 57-dB S/N at 20MS/s and 54-dB S/N at 30MS/s," IEEE Journal of Solid-State Circuits, Vol.36, No.4, pp.696-700, April 2001.pdf

    A17. Y.Sugimoto, "Low-Power and Low-Voltage Analog Circuit Techniques toward the 1 V Operation of Baseband and RF LSIs," IEICE Trans. Electron., Vol.E85-C, No.8, pp.1529-1537, August 2002 (Invited).pdf

    A18. H.Sakurai and Y.Sugimoto, "The Design of a 2.7 V, 200 MS/s, and 14-Bit CMOS D/A Converter with 63 dB of SFDR Characteristics for the 90 MHz Output Signal," IEICE Trans. Electron., Vol.E86-C, No.6, pp.1077-1084 , June 2003.pdf

    A19. Y.Sano, A.Takagi and Y.SugimotoGA Study of Effective Power-Reduction Methods for PDP Address-Driver Ics by Applying a Power-Dispersion SchemeGIEICE Trans. Electron., Vol.E86-C, No.8, pp.1774-1781, August 2003.pdf

    A20. Y.Sugimoto and S.Satoh, "A Study to Determine an Effective Ground-Shield Structure for a Silicon On-Chip Spiral Inductor," Journal of Japan Institute of Electronics Packaging, Vol.6, No.6, pp.473-480, September 2003.

    A21. Y.Sugimoto, "A Realization of a Below-1-V Operational and 30-MS/s Sample-and-Hold IC With a 56-dB Signal-to-Noise Ratio by Applying the Current-Based Circuit Approach," IEEE Transactions on Circuits and Systems-I, Vol.51,No.1, pp.110-117, January 2004. pdf

    A22. Y.Sugimoto and S.Kojima, "A 1 MHz, Synchronous, Step-down from 3.6 V to 1 V, PWM CMOS DC-DC Converter with more than 80 % of Power Efficiency," IEICE Trans. Electron., Vol.E87-C, No.3, pp.416-422, March 2004.pdf

    A23. S.Kawada and Y.Sugimoto, "A Bipolar ECL Comparator for a 4 GS/s and 6-Bit Flash A-to-D Converter," IEICE Trans. Electron., Vol.E87-C, No.6, pp.1022-1024, June 2004. (Letter) A24. H.Sakurai and Y.Sugimoto, "Analysis and Design of a Current-Mode PWM Buck Converter Adopting the Output-Voltage Independent Second-Order Slope Compensation Scheme," IEICE Trans. Fundamentals, Vol.E88-A, No.2, pp.490-497, February 2005.pdf

    A25. S.Kawada and Y.Sugimoto, "A 500-MHz and 60-dBĦCMOS Transimpedance Amplifier Using the New Feedforward Stabilization Technique," IEICE Trans. Electron., Vol.E88-C, No.6, pp.1285-1287, June 2005.pdf

    A26. Y.Sugimoto, Y.Gohda and S.Tanaka, "A Study to Realize a CMOS Pipelined Current-Mode A-to-D Converter for Video Applications," IEICE Trans. Electron., Vol.E89-C, No.6, pp.811-813, June 2006.pdf

    A27. H.Sakurai and Y.Sugimoto, "The Realization of an Area-Efficient CMOS Bandgap Reference Circuit with Less than 1.25 V of Output Voltage Using a Fractional VBE Amplification Scheme," IEICE Trans. Electron., Vol.E90-C, No.2, pp.499-506, February 2007.pdf

    A28. T.Choi, T.Sakamoto, and Y.Sugimoto, "A Study to Realize a 1-V Operational Passive ġ-Ģ Modulator by Using a 90 nm CMOS Process," IEICE Trans. Electron., Vol.E90-C, No.6, pp.1304-1306, June 2007. (Letter)pdf

    A29. H.Sakurai and Y.Sugimoto, "A Digitally Assisted Gain and Offset Error Cancellation Technique for a CMOS Pipelined ADC with a 1.5-bit Bit-Block Architecture," IEICE Trans. Fundamentals, Vol.E90-A, No.10, pp.2272-2279, October 2007.pdf

    A30. Y.Sugimoto and David G. Haigh, "A Current-Mode Circuit With a Linearized Input V/I Conversion Scheme and the Realization of a 2-V/2.5-V Operational 100-MS/s, MOS SHA," IEEE Transactions on Circuits and Systems-I, Vol.55, No.8, pp.2178-2187, September 2008.pdf

    A31. T.Sai and Y.SugimotoGA Near 1-V Operational, 0.18-um CMOS Passive Sigma-Delta Modulator with 77 dB of Dynamic RangeGIEICE Transactions on Electronics, Vol.E93-C, No.6, pp.747-754, June 2010.pdf

    A32. T.Sai and Y.SugimotoGA Current-Mode Buck DC-DC Converter with Frequency Characteristics Independent of Input and Output Voltages Using a Quadratic Compensation SlopeGIEICE Transactions on Electronics, Vol.E95-C, No.4, pp.677-685, April 2012.pdf

    A33. T.Sai, S.Sugimoto and Y.SugimotoGA Precision and High-Speed Behavioral Simulation Method for Transient Response and Frequency Characteristics of Switching ConvertersGIEICE Transactions on Electronics, Vol.E95-C, No.6, pp.1067-1076, June 2012.pdf


    Papers presented at International Conferences


    I1. Y.Sugimoto and T.Miyakawa, "The Efficient Circuit Design System for Analog Integrated Circuits," Digest of ICCE '82, pp.168-169, June 1982.

    I2. Y.Sugimoto, S.Mizoguchi, S.Komatsu and T.Yamashita, "A Monolithic 10-bit A/D and D/A Converter for PCM Audio Use," Digest of ICCE '84, pp.210-211, June 1984.

    I3. M.Nakamura, Y.Sugimoto, T.Watanabe and T.Sugimoto, "10 Bit 65Msps Glitch Free Video DAC," Digest of ICCE '85, pp.216-217, June 1985.

    I4. Y.Sugimoto and H.Hara, "BI/CMOS Interface Circuit in Mixed CMOS/TTL and ECL Use Environment," Extended Abstracts, 171st Siciety Meeting, vol.87-1, p.398, September 1987.

    I5. H.Iwai, "1.2 um Bi-CMOS Technology with High Performance ECL," Proceedings of ESSDERC '87, pp.29-32, September 1987.

    I6. H.Iwai, "0.8 um Bi-CMOS Technology with High ft Ion-implanted Emitter Bipolar Transistor," Proceedings of IEDM '87, pp.2-5, December 1987.

    I7. S.Mizoguchi, "Bi-CMOS Tracking Servo LSI for 8 mm VCR," Proceedings of CICC '88, pp.12.7.1-4, May 1988.pdf

    I8. Y.Sugimoto and S.Mizoguchi, "An Experimental Bi-CMOS Video 10bit ADC," Digest of 1988 VLSI, pp.129-130, August 1988.pdf

    I9. Y.Sugimoto, "A TV(UHF/VHF)/FM/AM Compatible Bi-CMOS Single Chip PLL IC," Digest of 1989 VLSI, pp.93-94, May 1989.pdf

    I10. H.Hara, "A 350ps 50k 0.8 um BiCMOS Gate Array with Shared Bipolar Cell Structure," Proceedings of CICC '89, pp.8.5.1-4, May 1989.pdf

    I11. K.Tsugaru, "A 10bit 40MHz ADC Using 0.8 um Bi-CMOS Technology," Proceedings of BCTM '89, pp.48-51, September 1989.pdf

    I12. K.Tsugaru, "A Single-Power-Supply 10-b Video BiCMOS Sample-and-Hold IC," Proceedings of ESSCIRC '89, pp.84-87, September 1989.pdf

    I13. S.Nitta, "A Variable Delay Generator for Deskew IC using ECL Gate Array," Digest of 1991 VLSI, pp.55-56, May 1991.pdf

    I14. Y. Sugimoto, "A 1.6V 10-bit 20MHz Current-mode Sample and Hold Circuit," Proceedings of 1995 IEEE International Symposium on Circuits and Systems, Volume 2 pp.1332-1335, May 1995.pdf

    I15. Y.Sugimoto and T.Iida, "A Current-mode, 3V, 20MHz, 9-bit equivalent CMOS Sample-and-Hold Circuit," Proceedings of Asia and South Pacific Design Automation Conference 1997 ( ASP-DAC '97 ), pp.685-686, January 1997.pdf

    I16. Y.Sugimoto and T.Ueno, "The Design of a 1V, 1GHz CMOS VCO Circuit with In-phase and Quadrature-phase Outputs," Proceedings of 1997 IEEE International Symposium on Circuits and Systems, Volume 1, pp.269-272, June 1997.pdf

    I17. Y.Sugimoto and T.Iida, "A Low-Voltage, High-Speed and Low-Power Full Current-mode Video-rate A/D Converter," Proceedings of the 23rd European Solid-State Circuits Conference, pp.392-395, September 1997.pdf

    I18. Y.Sugimoto and T.Hamasaki, "A 2V, 500MHz and 3V, 920MHz Low-Power Current-Mode 0.6ƒŹm CMOS VCO Circuit," Proceedings of 1998 Asia-Pacific Microwave Conference, pp.789-792, December 1998.pdf

    I19. Y.Sugimoto and S.Imai, "The Design of a 1V, 40MHz Current-mode Sample-and-hold Circuit with 10-bit Linearity, "Proceedings of 1999 IEEE International Symposium on Circuits and Systems, Volume 2, pp.II-132 - II-135, June 1999.pdf

    I20. Y.Sugimoto, "A 1.5 V, 30 Msps, 9- to 10-bit equivalent Current-mode CMOS Sample-and-hold Circuit," Proceedings of the 25th European Solid-State Circuits Conference, pp.378-381, September 1999.pdf

    I21. K.Murata, T.Hosaka and Y.Sugimoto, "Effect of a Ground Shield of a Silicon On-chip Spiral Inductor," Proceedings of 2000 Asia-Pacific Microwave Conference, pp.177-180, Paper No. 215, December 2000.pdf

    I22. Y.Sugimoto, "A 1V operational, 20Ms/s and 57dB of S/N, Current-mode CMOS Sample-and-hold IC," Digest of Technical Papers, 2001 Symposium on VLSI Circuits, pp.207-208, Paper No. 19-1, June 2001.pdf

    I23. Y.Sano, A.Takagi, T.Kawada, H.Inoue, K.Kariya, and Y.Sugimoto, "Reduction of Power Consumption in Address Driver ICs for PDP by Power Distributing Method," Digest of Technical Papers, 2001 SID International Symposium, pp.1228-1231, June 2001.

    I24. I.Furukawa and Y.Sugimoto, "A Synchronous, Step-down from 3.6V to 1.0V, 1MHz PWM CMOS DC/DC Converter," Proceedings of the 27th European Solid-State Circuits Conference, pp.96-99, September 2001.pdf

    I25. S.Tanaka, Y.Ghoda and Y.Sugimoto, "The Realization of a Mismatch-free and 1.5-bit Over-sampling Pipelined ADC," Proceedings of 2005 IEEE International Symposium on Circuits and Systems, C4P-T.8, pp.6194-6197, May 2005.pdf

    I26. H.Sakurai and Y.Sugimoto, "Design of a Current-mode, MOS, DC-DC Buck Converter with a Quadratic Slope Compensation Scheme," Proceedings of 48 th Midwest Symposium on Circuits and Systems, Vol.1, pp.671-674, August 2005. Digital Object Identifier 10.1109 / MWSCAS. 2005. 1594190.pdf

    I27. Y.Sugimoto, Y.Ghoda and S.Tanaka, "A 35MS/s and 2V/2.5V Current-mode Sample-and-Hold Circuit with an Input Current Linearization Technique," Proceedings of 2005 IEEE Asian Solid-State Circuits Conference, P2-20, pp.445-448, November 2005.pdf

    I28. Y.Hara, H.Sakurai and Y.Sugimoto, "A 2.5 GHz CMOS LC VCO with Improved Phase Noise Based on the Transformer Feedback Scheme," 2006 Asia-Pacific Microwave Conference (APMC 2006) Technical Programs, TH3F-5, December 2006.pdf

    I29. K.Umimura, H.Sakurai, and Y.Sugimoto, "A CMOS Current-mode DC-DC Converter with Input and Output Voltage-Independent Stability and Frequency Characteristics Utilizing a Quadratic Slope Compensation Scheme," Proceedings of the 33rd European Solid-State Circuits Conference, pp.178-181, September 2007.pdf

    I30. N.Yoshii, K.Mizutani and Y.Sugimoto, "A Current-mode ADC with Current Exchanging and Averaging Capabilities by Switching the Currents and Calculating Data in the Digital Domain," Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, MP-07, pp.209-212, September 2007.pdf

    I31. T.Ogino and Y.Sugimoto, "The Influence of Dummy Fills on an On-chip Spiral Inductor and their Optimized Placement Scheme," 2008 Asia-Pacific Microwave Conference (APMC 2008) Technical Programs, [Session name: Grounding & Manufacturing] J5-06, December 2008.pdf

    I32. C.Kawabata and Y.Sugimoto, "A Current-mode DC-DC Converter using a Quadratic Slope Compensation Scheme," Proceedings of the 14th Asia and South Pacific Design Automation Conference Microwave Conference (ASP-DAC 2009), Session 1-D, University Design Contest, Paper no. 1D-12, pp.113-114, January 2009.pdf

    I33. T.Sai and Y.Sugimoto, "A 14-bit MOS DAC with Current Sources free from Power-Line Voltage Drop and with Output Circuits free from Code-dependent Variable Time Constant," European Conference on Circuit Theory and Design 2009 (ECCTD 2009), CDROM pp.49-52, Session A1L-C3, August 2009.pdf

    I34. T.Sai and Y.Sugimoto, "Design of a 1-V Operational Passive Sigma-Delta Modulator," European Conference on Circuit Theory and Design 2009 (ECCTD 2009), CDROM pp.751-754, Session C2L-E4, August 2009.pdf

    I35. Y.Sugimoto, "A CMOS Current-mode Buck DC-DC Converter with a 240-kHz Loop Bandwidth and Unaltered Frequency Characteristics Using a Quadratic and Input-voltage-dependent Compensation Slope," ESSCIRC 2009, Proceedings of the 35th European Solid-State Circuits Conference, pp.460-463, September 2009.pdf

    I36. T.Sai and Y.Sugimoto, "A Method for Realizing a Fast Response Time for the Output Current Change of a MOS Current-mode Buck DC-DC Converter Which Utilizes a Quadratic and Vin-Dependent Compensation Slope," Proceedings of 2009 IEEE Asian Solid-State Circuits Conference, to be published, November 2009pdf

    I37. Y.SugimotoGA Highly Efficient Transient and Frequency-Response Simulation Method for Switching Converters without Using a SPICE-like Analog SimulatorGProceedings of 2010 IEEE International Symposium on Circuits and Systems, A6P-T.4, pp.1308-1311, May 2010.pdf

    I38. S.Sugimoto, M.Suzuki and Y.SugimotoGAccurate, High-Speed Simulation of Transient Response and Frequency Characteristics of Switching ConvertersG2010 IEEE Asia Pacific Conference on Circuits and Systems, RM4-S3 Special session, Paper ID 1569339121, December 2010.pdf

    I39 Y.SugimotoGLinearity and Intrinsic Gain Enhancement Techniques using Positive Feedbacks to Realize a 1.2-V, 200-MHz, +10.3-dBm of IIP3 and 7th-order LPF in a 65-nm CMOSGProceedings of the 37th European Solid-State Circuits Conference, pp.95-98, September 2011.pdf

    I40 Y.Hirano and Y.SugimotoGA MOS Current-Mode Boost DC-DC Converter with the Duty-Ratio-Independent Frequency CharacteristicsGProceedings of 2011 IEEE Asian Solid-State Circuits Conference, pp.49-52, November 2011.pdf

    I41 N.Ogawa and Y.SugimotoGA Low-voltage and Stable Phase Compensation Technique to realize an 99-dB,650-MHz and 1.8-V Theree-stage AmplifierGProceedings of 2012 IEEE International Symposium on Circuits and Systems, pp.2175-2178,May 2012.pdf


    Books


    B1. Title: "Analog to Digital Conversion Technique" Editors & Authors: Y.Sugimoto and A.Matsuzawa and etc. Publisher: Mimatsu Data Systems Data: October 1994 (In Japanese).

    B2. Title: "Understandable Analog Electronic Circuit" Author: Y.Sugimoto Page count: 176 papges Publisher: Ohm Corporation Data: February 1995 (In Japanese).

    B3. Title: "Electronics Handbook" Authors: Share Publisher: IEICE Data: 2000 (In Japanese).

    B4. Title: "Electric Handbook" Authors: Share Publisher: IEEJ Data: February 2001 (In Japanese).

    B5. Title: "Lecture and Practice of Electronic Circuit" Author: Y.Sugimoto, T.Shima and H.Tanimoto Page count: 231 papges Publisher: Nisshin Publishing Company Data: March 2003 (In Japanese).

    B6. Title: "Solving Electronic Circuit" Author: Y.Sugimoto Page count: 231 papges Publisher: Koudan-sha Data: June 2008 (In Japanese).


    Japanese Patents

    JP#1165121: "Amplifier Circuit," Y.Sugimoto

    JP#1291007: "BTL Amplifier Circuit," Y.Sugimoto

    JU#1477253: "Variable Gain Control Circuit," Y.Sugimoto

    JU#1497435: "Flip-Flop Circuit," Y.Sugimoto

    JP#1443293: "Variable Frequency Oscillator," Y.Sugimoto

    JP#1649394: "A Switch Circuit for the Sample-and-Hold Function," Y.Sugimoto

    JP#1653444: "The Input Circuit of an Analog-to-Digital Converter," Y.Sugimoto

    JP#1717958: "A Decoder Circuit for the Digital-to-Analog Converter," Y.Sugimoto

    JP#1738477: "Linear Clip Circuit," Y.Sugimoto

    JP#1745866: "Digital-to-Analog Converter Circuit," Y.Sugimoto

    JP#1748798: "Inverter Circuit," Y.Sugimoto

    JP#1750019: "Proportional Current Generation Circuit," Y.Sugimoto

    JP#1758355: "Sample-and-Hold Circuit," Y.Sugimoto

    JP#1758768: "Booth's Conversion Circuit," H.Sugiyama, Y.Sugimoto and Y.Kamatani

    JP#1862029: "Output Circuit," K.Tsugaru and Y.Sugimoto

    JP#1874400: "Full Adder Circuit," S.Shimizu, Y.Kamatani, Y.Sugimoto and H.Hara

    JP#1885730: "Output Circuit," H.Hara and Y.Sugimoto

    JP#1895476: "Level Conversion Circuit," S.Nitta and Y.Sugimoto

    JP#1943284: "ECL Circuit," Y.Sugimoto

    JP#1943292: "ECL Rogic Circuit," T.Sugoh and Y.Sugimoto

    JP#1952803: "Constant Voltage Circuit," S.Nitta and Y.Sugimoto

    JP#1982757: "Tri-State Buffer Circuit," H.Hara and Y.Sugimoto

    JP#2027484: "Counter Circuit," M.Takahashi, M.Nakamura and Y.Sugimoto

    JP#2105818: "Level Conversion Circuit," H.Sugiyama and Y.Sugimoto

    JP#2119554: "Semiconductor Equipment," H.Hara, Y.Sugimoto and T.Nagamatsu

    JP#2549729: "Semiconductor Integrated Circuit," H.Hara and Y.Sugimoto

    JP#3593261: "Hysteresis Comparator Circuit & Waveform Generator Circuit," M.Takai and Y.Sugimoto

    JSP#4183179: "Analog-to-Digital Converter," Y.Sugimoto

    JPA_2002163894: "Sample Hold Circuit and A/D Converter," S.Miyabe and Y.Sugimoto

    JPA_2002164746: "Cascode Amplifier Circuit and Folded Cascode Amplifier Circuit," S.Miyabe and Y.Sugimoto

    JPA_2002164750: "Differential Comparator Circuit," S.Miyabe and Y.Sugimoto

    JPA_2004095777: "Inductor Element," Y.Sugimoto

    JPA_2004320647: "Variable Delay Time Pulse Amplifier," Y.Sugimoto

    JPA_2005242450: "Constant Voltage and Constant Current Generation Circuit," Y.Sugimoto

    JPA_2006020441: "DC/DC Converter," Y.Sugimoto

    JPA_2008042275: "LC Oscillation Circuit," Y.Sugimoto

    JPA_2008227920: "Current Source Circuit, and Digital/Analog Converter," Y.Sugimoto and H.Sakurai


    US Patents

    USP#4,168,472: "Variable Gain Controller," Y.Sugimoto

    USP#4,492,934: "Voltage Controlled Oscillator with Linear Characteristic," Y.Sugimoto

    USP#4,499,429: "Variable Gain Control Circuit," Y.Sugimoto

    USP#4,558,363: "Gamma Correction Circuit," Y.Sugimoto

    USP#4,578,668: "Decoder for a D/A Converter," Y.Sugimoto

    USP#4,584,557: "Quantizer-subtractor Circuit," Y.Sugimoto

    USP#4,600,893: "Differential Amplifier with Improved Dynamic Range," Y.Sugimoto

    USP#4,626,794: "Amplifier Circuit Using a P Channel MOS Transistor," Y.Sugimoto

    USP#4,636,659: "Sample and Hold Circuit," Y.Sugimoto

    USP#4,695,750: "Voltage Level Converting Circuit," H.Hara, M.Nakamura and Y.Sugimoto

    USP#4,713,600: "Level Conversion Circuit," K.Tsugaru and Y.Sugimoto

    USP#4,718,035: "Logic Operation Circuit Having an Exclusive-OR Circuit," H.Hara and Y.Sugimoto

    USP#4,719,370: "BiCMOS High Speed Inverter Circuit," Y.Sugimoto

    USP#4,725,982: "Tri-state Buffer Circuit," H.Hara and Y.Sugimoto

    USP#4,733,110: "BICMOS Logical Circuits," H.Hara and Y.Sugimoto

    USP#4,740,907: "Full Adder Circuit Using Differential Transistor Pairs," S.Shimizu, Y.Kamatani, Y.Sugimoto and H.Hara

    USP#4,779,016: "Level Conversion Circuit," H.Sugiyama and Y.Sugimoto

    USP#4,782,251: "Level Conversion Circuit," K.Tsugaru and Y.Sugimoto

    USP#4,788,459: "Bi-CMOS Voltage Level Conversion Circuit," K.Tsugaru and Y.Sugimoto

    USP#4,798,980: "Booth's Conversion Circuit," H.Sugiyama, Y.Sugimoto and Y.Kamatani

    USP#4,798,981: "Input Circuit," K.Tsugaru and Y.Sugimoto

    USP#4,816,831: "Analog-digital Converter Realizing High Integration with High Resolution Ability," S.Mizoguchi, Y.Sugimoto and S.Shimizu

    USP#4,831,579: "Full Adder Circuit Having an Exclusive-OR Circuit," H.Hara and Y.Sugimoto

    USP#4,839,609: "Differential Amplifier," H.Hara and Y.Sugimoto

    USP#4,912,394: "Attenuator Circuit," Y.Sugimoto and H.Mafune

    USP#4,918,450: "Analog/digital Converter Circuit," H.Sugiyama and Y.Sugimoto

    USP#4,999,631: "High-precision and High-speed Analog/digital Converter Having Low Power Consumption," Y.Sugimoto

    USP#5,019,821: "Bias Circuit for a Subranging Analog to Digital Converter," Y.Sugimoto

    USP#5,034,630: "Logic Circuit for for Use in D/A Converter Having ECL-type Gate Structure," H.Sugiyama, M.Nakamura and Y.Sugimoto

    USP#5,066,996: "Channelless Gate Array with a Shared Bipolar Transistor," H.Hara, Y.Sugimoto and T.Nagamatsu

    USP#5,081,376: "Level Converter for Converting ECL-level Signal Voltage to TTL-level Signal Voltage," S.Nitta and Y.Sugimoto

    USP#5,101,125: "Semiconductor Integrated Circuit with Improved I/O Structure with ECL to CMOS to ECL Conversion," H.Hara and Y.Sugimoto

    USP#5,122,683: "ECL Circuit with Feedback Controlled Pull Down in Output," T.Sugoh and Y.Sugimoto

    USP#5,126,595: "BI-MOS Semiconductor Integrated Circuit," H.Hara and Y.Sugimoto

    USP#5,144,164: "BiCMOS Current Switching Circuit Having a Plurality of Resistors of a Specified Value," Y.Sugimoto, S.Mizoguchi and H.Mafune

    USP#5,146,116: "ECL Circuit with a Reduced Power Active Pulldown," Y.Sugimoto

    USP#5,146,118: "Bi-CMOS Logic Gate Circuits for Low-voltage Semiconductor Integrated Circuits," M.Nakamura and Y.Sugimoto

    USP#5,191,553: "Semiconductor Memory Having a Plurality of Ports," S.Mizoguchi and Y.Sugimoto

    USP#5,278,491: "Constant Voltage Circuit," S.Nitta and Y.Sugimoto

    USP#6,163,190: "Hysteresis Comparator Circuit Consuming a Small Current," M.Takai and Y.Sugimoto

    USP#6,429,695: "Differential Comparison Circuit," S.Miyabe and Y.Sugimoto

    USP#6,437,608: "Sample-and-Hold Circuit and A/D Converter," S.Miyabe and Y.Sugimoto

    USP#6,476,680: "Cascode Amplifying Circuit and Folded Cascode Amplifying Circuit," S.Miyabe and Y.Sugimoto


    European Patents

    EP-B1-0086958: "A Gamma Correction Circuit," Y.Sugimoto

    EP-B1-0087602: "Variable Gain Control Circuit," Y.Sugimoto

    EP-B1-0121234: "Decoder for a D/A Converter," Y.Sugimoto

    EP-B1-0144647: "Differential Amplifier," Y.Sugimoto

    EP-B1-0159654: "Amplifier Circuit," Y.Sugimoto

    EP-B1-0212004: "A Solid State Inverting Circuit Having a Bipolar Transistor for Rapidly Processing I/O Signals," Y.Sugimoto


    Korean Patent

    #41452: "Differential Circuit," H.Hara and Y.Sugimoto



    This is Sugimoto Lab. Status: 2012-10-26 update